1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to a ferroelectric memory device and a driving method thereof.
2. Description of the Related Art
A ferroelectric memory device is a semiconductor device having a MISFET structure and stores information in the form of spontaneous polarization of a ferroelectric material such as PZT (PbZnTiO.sub.3). Thus, a ferroelectric memory device realizes a high-speed, non-volatile storage of information. In a ferroelectric memory device, it is further possible to conduct a writing of information with a commonly used supply voltage of 3.3V or 5 V, while this feature is a significant advantage over a flash memory device that requires a voltage of as high as 10-20 V for writing information. Particularly, the ferroelectric memory device of the so-called MFS (metal-ferroelectric-semiconductor) FET, which has a simple construction in that only a single MISFET is used in a memory cell, is suitable for constructing a large storage-capacity non-volatile semiconductor memory integrated circuit by integrating the FETs with a large integration density.
Meanwhile, the inventor of the present invention has proposed a novel ferroelectric memory cell transistor in the Japanese Laid-open Patent Publication 9-82905.
FIG. 1 shows the construction of a ferroelectric memory cell transistor 20 according to the foregoing prior art.
Referring to FIG. 1, the ferroelectric memory cell transistor 20 is formed on a Si substrate 21 and includes a p-type well 22 formed on the Si substrate 21, n.sup.+ -type diffusion regions 22A and 22B formed in the p-type well 22 as the diffusion region of the MFS-FET, and a channel region 22C formed in the well 22 between the diffusion regions 22A and 22B as the channel region of the MFS-FET.
Further, the memory cell transistor 20 includes a floating electrode 23B of Pt, and the like, on the channel region 22C, with an SiO.sub.2 film 23A intervening between the floating electrode 23B and the surface of the well 22, and a ferroelectric film 23C of PZT, and the like, is formed on the floating electrode 23B. The ferroelectric film 23C carries thereon a gate electrode 23D of polysilicon, and the like. Thereby, the device of FIG. 1 constitutes a MFS-FET having a PZT film for storage of information.
Further, the gate electrode 23D is connected to a word line WL and the diffusion region 22A is connected to a bit line BL, wherein it should be noted that the bit line BL is connected also to the well itself in the foregoing conventional example of FIG. 1. Further, the construction of FIG. 1 includes a p-type diffusion region 22D in the diffusion region 22B and the diffusion region 22B forms a part of the diode.
FIG. 2 shows the circuit diagram of the ferroelectric memory device that uses the ferroelectric memory cell transistor 20 of FIG. 1.
Referring to FIG. 2, there is provided a word line WL.sub.0 selected by a row selection transistor Row such that the word line WL.sub.0 is connected to a gate electrode corresponding to the gate electrode 23D of FIG. 1 and such that the word line WL.sub.0 is also connected to the diffusion region 22B via a diode formed by the p-type diffusion region 22B of FIG. 1. Further, a bit line BL.sub.0 is connected to the diffusion region 22A of FIG. 1 and further to a sense amplifier S/A via a column selection transistor Col. It should be noted that there are provided a word line WL.sub.1 and a bit line BL.sub.1 adjacent to the word line WL.sub.0 and BL.sub.0 and a memory cell transistor not shown is connected to the word line WL.sub.1 and BL.sub.1 similarly to the memory cell transistor 20.
In the construction of FIG. 2, a writing of information into the memory cell transistor 20 is conducted by selecting the word line WL.sub.0 and the bit line BL.sub.0 via the row selection transistor Row and the column selection transistor Col and by applying a write voltage across the gate electrode 23D and the p-type well 22. As a result, the information is recorded in the ferroelectric film 23B in the form of spontaneous polarization.
When reading information, the word line WL.sub.0 is selected by the row selection transistor Row and a read voltage is applied to the gate electrode 23D. Simultaneously, the read voltage is applied to the diffusion region 22B of the memory cell transistor 20 via a diode formed by the diffusion regions 22B and 22D. Thus, the voltage appearing on the bit line BL.sub.0, which is selected by the column selection transistor Col, is detected by the sense amplifier S/A cooperating with the bit line BL.sub.0.
In the memory cell transistor 20 of FIG. 1, it should be noted that the bit line BL has to be connected to the p-type well 22, and thus, there is provided a contact hole exposing the p-type well in an insulation film (not shown) that covers the memory cell transistor 20, adjacent to the diffusion region 22A. However, such an additional contact hole causes an increase in the area of the memory cell transistor and decreases the integration density of the ferroelectric memory integrated circuit formed by integrating the memory cell transistors 20. In relation to the integration of the memory cell transistors, it should be noted that the construction of FIG. 1 requires the well 22 that acts as a device isolation structure.